As data center switch silicon, AI accelerator fabrics, and optical modules race toward 1.6T and beyond, 224G PAM4 PCB design has shifted from theoretical white paper to production reality. Unlike earlier NRZ interfaces, 224G PAM4 transmits four-level pulse amplitude modulation at 112 GBaud, squeezing more bits per symbol but reducing voltage margins to roughly one-third of NRZ. This means every milliohm of copper resistance, every discontinuity in a via, and every variation in dielectric constant directly affects the bit error rate. To build these channels successfully, PCB teams must integrate signal integrity, material science, and manufacturing tolerances from the first stackup decision rather than treating layout as a post-simulation exercise.
For hardware teams working on next-generation backplanes, DSP-based line cards, or co-packaged optics, the transition is not simply a speed bump. It forces a fundamental rethink of how high-speed lanes are modeled, routed, and fabricated. The challenge is no longer just maintaining a 100 Ω differential impedance; it is preserving an eye opening that may be only a few millivolts high at the receiver.
Why 224G PAM4 Radically Tightens PCB Channel Budgets
The move from 112G PAM4 to 224G PAM4 doubles the baud rate from 56 GBaud to 112 GBaud. The Nyquist frequency, which represents the fundamental signal content, rises to 56 GHz, and meaningful harmonic energy can extend well beyond 70 GHz depending on rise time and equalization. At these frequencies, the PCB channel is no longer a benign interconnect. It behaves like a distributed microwave network where insertion loss, return loss, and crosstalk all consume a finite signal-to-noise budget.
PAM4 signaling is particularly sensitive because it encodes two bits in four amplitude levels. Compared with NRZ, PAM4 suffers an SNR penalty of approximately 9.5 dB for the same symbol amplitude. That penalty would be manageable if the channel were nearly ideal, but a 224G electrical path is far from ideal. Dielectric losses rise roughly linearly with frequency, while copper roughness losses increase even faster at high frequencies. Reflections from via transitions, connector launches, and BGA breakout discontinuities can create notches in the channel response that no receiver equalization can fully recover. Crosstalk from densely escaped differential pairs adds random noise that further erodes the eye.
In practice, a 224G PAM4 link may allow an insertion loss budget of 30 dB or more at the Nyquist frequency, but only when the PCB is designed to control every discontinuity. A 1.6T optical transceiver with eight 224G electrical lanes may have less than 25 mm of host PCB breakout, yet an unoptimized via stub or a single poorly placed ground return can consume 2–3 dB of margin. Similarly, an 800G switch line card with hundreds of high-speed lanes cannot tolerate fabrication drift in line width, dielectric thickness, or layer registration. This is why 224G PAM4 PCB design must treat channel simulation, material validation, and via optimization as parallel activities from the very beginning.
Laminate Selection and Stackup Architecture for 224G PAM4 PCBs
Material selection is the single most important early decision in 224G PAM4 PCB design. At 56 GHz, conventional FR-4 is almost unusable for long high-speed runs because its dielectric loss and moisture absorption create excessive attenuation and phase variation. Instead, ultra-low-loss resin systems based on hydrocarbon, PPE/PPO, or PTFE formulations are required. These materials typically offer a dielectric constant between 3.0 and 3.7 and a dissipation factor in the range of 0.0015 to 0.004 at 10 GHz, depending on the glass style and resin system. Lower Dk reduces propagation delay and crosstalk, while lower Df minimizes signal attenuation per inch.
However, dielectric loss is only part of the problem. Copper roughness becomes a major contributor to insertion loss at 112 GBaud. Traditional electrodeposited copper with high-profile teeth causes severe skin-effect resistance because the signal current must travel along a rough surface. For 224G channels, fabricators must use low-profile or very low-profile copper foils with roughness values below approximately 2 µm Rz, and in many cases below 1.5 µm Rz. Rolled annealed copper or smooth reverse-treated foils are commonly preferred. The combination of ultra-low-loss resin and smooth copper can reduce insertion loss by several decibels per inch compared with standard high-speed laminates.
Stackup architecture must also be symmetrical to prevent warpage and to keep impedance predictable. High-speed layers are normally placed on the top and bottom of the board, directly adjacent to solid ground reference layers. This minimizes the return path discontinuity and keeps the dielectric thickness tight. A hybrid stackup is often used to balance cost and performance: ultra-low-loss cores and prepregs are assigned to the 224G routing layers, while standard low-loss materials are used for lower-speed digital and power distribution layers. Engineers must also evaluate glass weave effects. At 56 GHz, the periodic variation in Dk from standard woven glass can create intra-pair skew and mode conversion. Spread glass, low-Dk glass, or routing at an angle to the weave pattern helps average these variations.
Routing, Via Design, and Signal Integrity Sign-Off for 224G PAM4
Once the stackup is defined, the next challenge is translating it into layout rules that preserve signal integrity. Differential pairs must maintain tight impedance tolerance, typically ±5% or better. But impedance is not enough; intra-pair length matching must be held to extremely small values, often under 1 mil, because phase mismatch between the positive and negative legs converts differential signal into common-mode noise and increases radiation. Pair-to-pair spacing must be significantly larger than in previous generations. Group spacing of at least 3–5 times the line width, and often more, is required to limit far-end crosstalk. In dense escape areas, this spacing rule conflicts with routability, so designers must rely on ground stitching vias, careful layer assignment, and shorter parallel runs to manage crosstalk.
Via design is equally critical. A through-hole via with an unused portion creates a resonant stub that can produce a deep insertion loss notch near the Nyquist frequency. For 224G signals, through-hole vias almost always require backdrilling to remove the stub, leaving only a minimal remaining length. The backdrill depth must be controlled within tight tolerances to avoid cutting into the signal trace or leaving excessive stub. Blind and microvias are also used in high-layer-count boards, particularly under large ASICs and optical engines. Via pads should use non-functional pad removal, oversized antipads, and carefully placed ground vias to provide a continuous return path. A missing ground via next to a signal via can create a discontinuity that is far more damaging than a few extra millimeters of trace length.
Signal integrity sign-off for 224G PAM4 cannot rely on rule-of-thumb checks alone. Designers must simulate full channel models, including package, breakout, via transitions, connector launches, and receiver termination. These models should be correlated with test coupons and measured S-parameters. In an 800G switch line card, escaping a large ASIC with hundreds of high-speed lanes may require three or four routing layers placed adjacent to ground references, with every via array simulated for via-to-via coupling and crosstalk. Power integrity also matters: noise on the SerDes supply can degrade jitter and reduce the available eye margin. Low-impedance power delivery, dedicated decoupling for PLLs, and quiet supply islands are essential.
Manufacturing tolerances are part of the link budget. Etch variation, layer registration, via drill wander, and backdrill depth accuracy all influence impedance and insertion loss. A strong 224G PAM4 PCB design flow therefore includes statistical simulation across process corners, test structures for material Dk/Df extraction, and design rules that remain manufacturable in volume. Surface finish selection must also be evaluated, since thick nickel in ENIG finishes can increase insertion loss at high frequencies. Smoother finishes such as ENEPIG or immersion tin are often preferred for high-speed layers. By combining simulation, material control, and fabrication-aware layout, teams can build reliable channels that leave enough margin for real-world system noise and thermal variation.
